Over 35 years in High Performance Computing and Parallel Computing.
Author/coauthor of ten programming books, numerous papers and blogs.
Expert on Supercomputer architectures and HPC programming. Strong Communicator.
Professional Experience
Intel Corporation
November 2020 – present
Engineer
Corporate qualified spokesperson (media trained) for Intel, 1998-2016, 2020-.
James Reinders Consulting LLC
August 2016 – November 2020
HPC and ML/AI Consultant
- Expert consulting
- Blogging
- Technical writing, Teaching, White Papers
- High Performance Machine Learning
Intel Corporation
February 1989 – June 2016
Intel Achievement Award Recipient, Intel’s highest honor.
Parallel Programming Models Architect for Intel’s HPC Business.
Key contributor for two of the longest standing #1 computers in history: ASCI Red (#1 for June 1997-November 2000) and Tianhe-2A (#1 for June 2013-June 2016).
Author/editor of ten technical books (while at Intel, two more post-Intel, two more since rejoining Intel)
HPC Technical Communications Expert: Public Face for Intel to High Performance Computing (HPC) Software Developers, Corporate qualified spokesperson for Press and Analysts.
Business Architect of Intel’s Software Tools Business (propelling Intel from obscurity to a leader in software development tools, with a powerful channel and sales force).
Official roles and titles during tenure at Intel:
Parallel Programming Model Architect and Evangelist, Director, October 2010-June 2016.
Evangelist and Director of Marketing & Sales for Software Development Tools, 2000-2010
Technical Marketing and Customer Support Manager – Intel Software Development Tools, Pentium 4 and Itanium Software Development Systems, 1998-2000
Project lead and manager Intel Fortran Compiler and C/C++ Frontend teams, 1995-1998
Senior Systems Architect ASCI Red Project (world’s first TeraFLOP supercomputer), Pentium Pro Compilers, and 64-bit Architecture Pathfinding, 1992-1995
Compiler Engineer and Team Lead, iWarp, Systolic Array Supercomputer, Compiler liaison to Carnegie Mellon University, 1989-1992
Corporate qualified spokesperson (media trained) for Intel, 1998-2016, 2020-.
Selected Publications
Books
- Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL, Apress, 2020
- Pro TBB: C++ Parallel Programming with Threading Building Blocks, Apress, 2019
- Intel Xeon Phi Processor High Performance Programming – Knights Landing Edition, Morgan Kaufmann, 2016
- High Performance Parallelism Pearls, Volume Two, Morgan Kaufmann, 2015
- High Performance Parallelism Pearls, Volume One, Morgan Kaufmann, 2015
- Multithreading for Visual Effects, CRC Press, 2014, co-author with other technical leaders (and friends) from Dreamworks Animation Pixar, AMD, Google, SideFX
- Intel Xeon Phi Coprocessor High Performance Programming, Morgan Kaufmann, 2013. Also translated to Japanese (2014) and Chinese (2014).
- Structured Parallel Programming, Morgan Kaufmann, 2012. Also translated to Japanese (2013).
- Intel Threading Building Blocks – Outfitting C++ for Parallelism, O’Reilly Press, 2007. Also translated to Japanese (2008), Chinese (2009) and Korean (2010). Sole author.
- VTune Performance Analyzer Essentials, Intel Press, 2005. Sole author.
Contributor to books:
- Authored entries on Systolic Arrays and Warp and iWarp, Encyclopedia of Parallel Computing, Padua, David (Ed.), Springer Publishing, 2011.
- Author of three chapters in Multi-Core Programming, Akhter, Shameem and Roberts, Jason Gross, Intel Press, 2006.
- Author of three chapters in Itanium Architecture for Software Developers, Intel Press, 2000.
- Contributor to book iWarp: Anatomy of a Parallel Computing System, Gross, T. and O’Hallaron, D., MIT Press, 1998.
Non-book publications:
- Editor of Intel Parallel Universe quarterly magazine. April 2009 (Issue 1) to Q3 2016 (Issue 25).
- Intel whitepapers, blogs and introductory material for publications, 1989-2016.
- Hardware and Systems. Reinders, J., in Information Technology Methoden und innovative Anwendungen der Informatik und Informationstechnik, 55(3), pp. 86-90. 2013.
- Only the first steps of the parallel evolution have been taken thus far, Reinders, J., Facing the Multicore-Challenge II, Springer, pp1-9, 2012.
- Rules for Parallel Programming for Multicore, Reinders, J., Dr.Dobbs Journal, Sept. 5, 2007
- Modelling Instruction-Level Parallelism for Software Pipelining, Adl-Tabatabai, A. and Gross, T. and Lueh, G. and Reinders, J., in Proc. IFIP WG10.3 (Concurrent Systems) Working Conf. on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, pp. 321-330. IFIP WG 10.3, North Holland, Orlando, FL., Jan 1993.
- “H-150 Speed-up Modifications,” REMark Magazine (HeathkitUser Group), November 1987, pp 44,47,56.
- “More Undocumented Z80™ Opcodes,” Lifelines Software Magazine, August 1982, pp 10-15.
- “Random Numbers for Microsoft BASIC,” Lifelines SoftwareMagazine, August 1981, pp 26-27.
Selected Teaching/Speaking Experience
- Argonne Training Program on Extreme-Scale Computing (ATPESC) invited speaker, 2017, 2016, 2015, and 2014.
- OpenMPCon Keynote speaker for inaugural conference, September 2015
- SIGGRAPH tutorial “Multithreading for Visual Effects” co-presenter in 2013 and 2015. Published the 2013 course as a book after being approached by publisher who sat in on the tutorial.
- Keynote speaker at IXPUG 17 in Austin Texas
- Moderator for Panel “Industry Panel: New Paradigm in Computing: What Should Developers Know?”
- SC17 Tutorial “SC17 Tutorial “Programming your GPU with OpenMP: A hands-on Introduction,” co-presenter.
- SC16 Tutorial “Programming your GPU with OpenMP: A hands-on Introduction,” co-presenter.
- SC13 Tutorial “Structured Parallel Programming with Patterns,” co-presenter.
- SC11 Workshop “Understanding Intel’s Parallel Programming Models,” co-presenter.
- Intel HPC Developer Conferences 2015: U.S., UK, India, Japan, Korea, China. Overall technical chair, speaker and MC for U.S.
- Intel Developers Forum (IDF), technical presentations every year 2003-2011 and in 2013 and 2015, multiple times “Outstanding Speaker” (top 10). Coaches speakers for most recent IDFs. Also taught courses at IDF events in Beijing, Seoul and Taiwan.
- Intel Sales and Marketing Conference (ISMC), United States, more than 10 years as an instructor.
- Multicore World, 2012, New Zealand, keynote speaker
- LCA2010/Multicore World, New Zealand, keynote speaker
- Apple World-Wide Developers Conference (WWDC), San Francisco, invited external speaker, 2007, 2008.
- China Software Developers Network Conference, Beijing, invited keynote speaker, 2007.
- Evans Data Corporation Developer Relations Conference, San Jose, invited keynote speaker 2009, 2010, 2011.
- Microsoft Professional Developer’s Conference (PDC), Los Angeles, invited external speaker and panelist, 2008, 2009.
- Finnish Multicore Days 2011 Conference, Stockholm, invited speaker and panelist, 2011.
- Swedish Institute of Computer Science, Multicore-Days 2008 Conference, Stockholm, invited speaker, 2008.
- Sony Corporation, Annual Technical Summit, Tokyo, invited keynote speaker, 2007.
- Customer training – multi-day technical training classes many locations around the world since 1987, hundreds of hours of teaching. Includes helping organize and deliver multiple hands-on courses for programming Intel Xeon Phi, ranging from 2 to 5 day long classes.
- Customer and partner visits – numerous technical and business related presentations at events including user group meetings.
- Taught sections of parallel programming classes, as a guest lecturer, at multiple universities around the U.S. Also – a guest speaker in college classes in New Zealand, China, Germany, UK, Canada and Mexico.
- School visits – classroom visits, especially during National Engineers Week, to motive/excite young minds about engineering.
- Parallel Programming for High School Students – Brooklyn Technical High School.
- Taught Intel employee development classes on constructive confrontation, situational leadership, dealing with the press at tradeshows; invited speaker at Intel Manager Training courses.
Employment before Intel
Software Project Lead Warp Compilers / GE Radar Systems Division; Syracuse, New York
C and LISP programming, customer training and support
May 1987-February 1989
Teaching Assistant / University of Michigan; Ann Arbors, Michigan
Lectures, grading, labs, office hours; graduate compiler construction, interactive computer graphics, discrete mathematics, data structures, and digital computer engineering lab classes.
September 1983-May 1987
Computer programming summer jobs during high school and college
LISP and C programming; Autonomous Mobile Robot Guidance Systems; 3D modeling and visualization.
General Motors Research, Computer Science; Warren, Michigan / Summers 1986 & 1985
C programming; Voice digitalization & cataloguing; telephone audio response systems
Votrax Incorporated – Voice Synthesis; Troy, Michigan / Summers 1984 & 1982
C and Forth programming; engine emission collection, calibration and analysis
Ford Scientific Research Labs – Engine test; Dearborn, Michigan / Summer 1983
DATABUS(PL/B) programming, customer support; small business accounting and job costing
Account Systems Incorporated; Bloomfield Hills, Michigan / Summer 1981
C and WD16000 assembly programming, customer support; restaurant PoS with central data collection and analysis
Alpha Software Consultants; Detroit, Michigan / Summer 1980
BASIC programming, customer support; small business accounting and job costing
Account Systems Incorporated; Bloomfield Hills, Michigan / Summer 1979
University Education
M.S.E. 1987: University of Michigan, Computer Engineering, summa cum laude
B.S.E. 1985: University of Michigan, Computer Engineering, cum laude
B.S.E. 1985: University of Michigan, Electrical Engineering, cum laude
U.S. Patents Issued
- U.S. Patent 6,698,011, 02-24-04, Isolation of program translation failures, co-inventors Joe Wolf III and Matt Frazer.
- U.S. Patent 6,535,584, 03-18-03, Detection and exploitation of cache redundancies.
- U.S. Patent 6,467,000, 10-15-02, Sideband transfer of redundancy bits for reduction of redundant cacheline transfers.
- U.S. Patent 6,044,437, 03-28-00, Method for generating and transferring redundancy bits between levels of a cache memory hierarchy.
- U.S. Patent 5,897,660, 04-27-99, Method for managing free physical pages that reduces trashing to improve system performance, co-inventor Joe Bonasera.
- U.S. Patent 5,819,088, 10-06-98, Method and apparatus for scheduling instructions for execution on a multi-issue architecture computer.
Keywords for areas of expertise
- high-performance computing (HPC)
- multicore processors
- many-core processors
- accelerators
- field-programmable gate arrays (FPGAs)
- compilers
- compiler optimization technology
- software optimization
- software tools
- operating systems
- GPGPUs
- GPU programming
- SIMD
- Vectorization
- CPUs
- CPU defects or design issues (e.g., FDIV, Spectre, Meltdown)
- computer security
- real time computing
- machine learning
- artificial intelligence (AI)
- programming languages
- computer science
- power efficiency
- performance portability for applications
- teaching
- technical communications
- technical marketing
- software distribution channels
- international software community (well-travelled, well connected)